1. Field Of the Invention
The invention relates to the video controller of the personal computer and workstation technology, particularly with respect to a video controller for supporting both VGA and EGA operating modes, and more specifically, the Architecture Extended (AX) Japanese EGA (JEGA) mode.
2. Description of the Prior Art
Three different architectures are presently utilized for the implementation of video controllers; viz., the VGA and enhanced VGA standard, the EGA standard and the Architecture Extended (AX) standard. The AX standard was developed for controlling the display of Japanese characters and utilizes two EGA video controllers operating substantially independently with respect to each other. The standard VGA video controller, as well as the standard EGA video controller, requires 256 kilobytes (KB) of video memory whereas extended VGA requires 512 KB of video memory. The AX standard requires two independent video memory banks of 256 KB each for the two EGA video controllers, respectively, utilized to implement the standard. The EGA convention supports a resolution of 640.times.350 pixels with 16 colors from a palette of 64 while standard VGA supports 256 simultaneous colors from a palette of 256 K (262,144) colors with resolution formats ranging to 640.times.480 pixels. Extended VGA supports resolution formats of 800.times.600 pixels and 1024.times.768 pixels, in some instances with 256 simultaneous colors.
The video memory is utilized by the controller for such functions as storing and manipulating character codes and character fonts and for providing multiple graphic frame buffers. The enhanced VGA architecture utilizes the full 512 KB of video memory primarily in generating high resolution graphics over a wide range of simultaneous colors. Typically, video memory is implemented utilizing Dynamic Random Access Memory chips (DRAM). In a well known manner, such DRAM elements utilize row and column addressing with the row and column addresses sequentially strobed into the memory chips by Row Address Strobes (RAS) and Column Address Strobes (CAS). Data is written to the memory by a Write Enable (WE) signal and read from the memory by an Output Enable (OE) signal.
The EGA video controller memory architecture, interface and bus protocol are significantly different from that of the VGA video controller. The EGA controller provides two independent eight-bit memory buses coupled to separate memory banks of 128 KB each. The buses carry time multiplexed address and data signals. The EGA controller applies the RAS and CAS signals to the full 256 KB of memory and applies the OE read signals transverse to the memory banks in a direction perpendicular to the direction of the buses. Any byte can be read from either bank by appropriate energization of the buses and OE lines. The EGA controller utilizes separate WE lines to write access any byte of the memory.
The VGA controller, on the other hand, utilizes separate address and data buses, the address bus being eight bits wide (with a ninth bit for the enhanced VGA capabilities) and the data bus sixteen bits wide. The address and data buses are connected to the full 256 KB of memory with individual RAS and CAS lines connected to strobe separate 128 KB memory banks. Separate OE lines run in the same direction through the memory as the RAS and CAS lines and during a memory read, two bytes are accessed and applied to the sixteen-bit wide data bus. Individual bytes are write accessed by individual WE lines. The ninth address line functions as a bank select between two 256 KB memory banks providing a total of 512 KB of accessable memory.
It is thus appreciated that in the VGA mode, access to the locations of the memory are primarily effected by selective application of the RAS, CAS, OE and WE signals. During a read operation, sixteen bits (two bytes) are accessed. In the EGA mode, on the other hand, memory locations are accessed by application of address signals to the appropriate memory bus and selective application of OE and WE signals. These diverse memory interfaces indicate the use of separate and independent memories for VGA and for EGA.
Thus, in the prior art, video controller boards required a separate memory array for each controller. If a VGA video controller board were required, 256 KB of video memory would be utilized for standard VGA or 512 KB of video memory would be utilized for enhanced or extended VGA modes. If an EGA video controller board were desired, 256 KB of video memory would be utilized for each EGA controller. If an AX compatible board is desired, two EGA video controllers are utilized with two independent banks of 256 KB of video memory for a total of 512 KB of video memory.
If it is desired to construct a video controller board that supports both AX/EGA and enhanced VGA modes, the two EGA controllers for the AX modes would require two respective dedicated banks of 256 KB of video memory each while the enhanced VGA controller would require an additional 512 KB of video memory for a total board memory requirement of 1024 KB or one megabyte of video memory. It is appreciated that DRAM memory chips are very expensive, thus significantly increasing the cost of such combination systems.
The apparatus of said Ser. No. 07/715,207 embodies the AX standard and enhanced VGA utilizing two diverse video controller memory architectures, that of the Chips And Technologies (C+T) 435 EGA controller and the Western Digital (WD) PVGA1B VGA controller. The AX Japanese video standard implemented by the system of said Ser. No. 07/715,207 utilizes two C+T 435 EGA controllers requiring independent memory banks of 256 KB each. The WDPVGA1B VGA controller requires 512 KB of video memory. Thus, conventional design approaches indicate, for the reasons given above, that two independent memory arrays of 512 KB each would be required for the two entirely different video circuits that utilize different and incompatible video controller memory architectures, memory interfaces, bus protocols and bus structures. A total of one megabyte of expensive video memory would normally be utilized to satisfy the requirements of this design.